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Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL

Das, S.R. and Jin, L. and Assaf, Mansour and Biswas, S.N. and Petriu, E.M. (2012) Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL. World Journal of Engineering, 9 (6). pp. 519-528. ISSN 1708-5284

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Abstract

The implementation of fault testing environment for embedded cores-based digital circuits is a challenging endeavor. The subject paper aims developing techniques in design verification and test architecture utilizing well-known concepts of hardware and software co-design. There are available methods to ensure correct functionality, in both hardware and software, for embedded cores-based systems but one of the most used and acceptable approaches to realize this is through the use of design-for-testability (DFT). Specifically, applications of built-in selftest (BIST) methodology in testing embedded cores are considered in the paper, with specific implementations being targeted towards the International Symposium on Circuits and Systems (ISCAS) 85 combinational benchmark circuits.

Item Type: Journal Article
Subjects: T Technology > T Technology (General)
Divisions: Faculty of Science, Technology and Environment (FSTE) > School of Engineering and Physics
Depositing User: Mansour Assaf
Date Deposited: 02 May 2013 11:18
Last Modified: 21 Jul 2016 11:39
URI: http://repository.usp.ac.fj/id/eprint/5790
UNSPECIFIED

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