Islam, Riazul and Sharif, Kazi and Haque, Mahbubul and Biswas, Satyendra and Das, Sunil and Assaf, Mansour and Petriu, Emil (2017) A low power dynamic logic with nMOS based resistive keeper circuit. [Conference Proceedings]
Full text not available from this repository. (Request a copy)Abstract
Designing VLSI circuit using dynamic logic is one of the most area efficient techniques. However, the performance of the dynamic logic is not so promising due to longer time delay and higher leakage power. This research proposes a new model of dynamic logic by incorporating nMOS based resistive gate circuit. The proposed circuit reduces the contention time delay and the leakage power. Extensive simulation results using LTSpice tools demonstrate the validity and superiority of the proposed circuit.
| Item Type: | Conference Proceedings |
|---|---|
| Subjects: | T Technology > T Technology (General) |
| Divisions: | Faculty of Science, Technology and Environment (FSTE) > School of Engineering and Physics |
| Depositing User: | Mansour Assaf |
| Date Deposited: | 21 Aug 2017 00:21 |
| Last Modified: | 21 Aug 2017 00:21 |
| URI: | https://repository.usp.ac.fj/id/eprint/10062 |
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