Das, S.R. and Jun-Feng, L. and Nayak, A. and Assaf, Mansour and Petriu, E.M. and Biswas, S.N. (2013) Circuit architecture test verification based on hardware software co-design with ModelSim. IETE Journal of Research, 59 (2). pp. 132-140. ISSN 0377-2063
Full text not available from this repository.Abstract
In view of the recent paradigm shift from system-on-board to designs embracing embedded cores-based system-on-chips (SOCs), the complexity of digital circuits has enormously increased. This growing complexity has resulted in a huge challenge in developing their appropriate and efficient fault testing environment. Despite significant efforts directed toward implementing effective testing strategies of very large scale integrated circuit chips with reasonable cost, new frontiers emerged with advances in technology. The subject paper endeavors to develop method to test verify circuit architecture under hardware software co-design environment, targeting specifically embedded cores-based SOCs. The concept of design-for-testability is utilized in the paper together with ModelSim simulation and verification tool to test synthesize the entire design. Some simulation results on the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits are also included with a comparison of the results with some earlier works.
| Item Type: | Journal Article |
|---|---|
| Subjects: | T Technology > T Technology (General) |
| Divisions: | Faculty of Science, Technology and Environment (FSTE) > School of Engineering and Physics |
| Depositing User: | Mansour Assaf |
| Date Deposited: | 08 Jun 2013 03:28 |
| Last Modified: | 15 Jun 2016 02:28 |
| URI: | https://repository.usp.ac.fj/id/eprint/5902 |
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