Koripella, R. and Das, S.R. and Morton, S. and Biswas, S.N. and Ozkarahan, I. and Assaf, Mansour (2013) High speed S - box architecture for advanced encryption standard. [Conference Proceedings]
Full text not available from this repository.Abstract
The advanced encryption standard (AES) is currently
recognized as one of the most popular cryptographic
algorithms. The substitution block, better known as S-Box,
is the key element in this encryption algorithm. Various
schemes have been put forward in the past to construct S-
Box, most of which are concerned with the reduction in the
chip area and increasing the speed of operations. This
paper presents realization of an area efficient S-Box
structure based on Galois field arithmetic that is also
optimized for speed. In the paper, we discuss implementation details of our proposed S-Box using very high speed integrated circuit (VHSIC) hardware description language (VHDL) and its comparison with the existing S-Box architectures. The results on simulation validate the merits of the suggested research. The S-Box architecture herein has been realized in Xilinx.
| Item Type: | Conference Proceedings |
|---|---|
| Subjects: | T Technology > T Technology (General) |
| Divisions: | Faculty of Science, Technology and Environment (FSTE) > School of Engineering and Physics |
| Depositing User: | Mansour Assaf |
| Date Deposited: | 23 Apr 2014 05:21 |
| Last Modified: | 21 Jun 2016 00:15 |
| URI: | https://repository.usp.ac.fj/id/eprint/7268 |
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