Low - level logic fault testing ASIC simulation environment

Assaf, Mansour and Moore, L-A. and Das, S.R. and Biswas, S.N. and Morton, S. (2014) Low - level logic fault testing ASIC simulation environment. World Journal of Engineering, 2 (3). pp. 279-286. ISSN 1708-5284

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Abstract

A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed
into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.

Item Type:	Journal Article
Subjects:	T Technology > T Technology (General)
Divisions:	Faculty of Science, Technology and Environment (FSTE) > School of Engineering and Physics
Depositing User:	Mansour Assaf
Date Deposited:	10 Sep 2014 00:58
Last Modified:	04 May 2016 00:57
URI:	https://repository.usp.ac.fj/id/eprint/7574

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